Standby current erasion circuit of dram

ABSTRACT

The present invention discloses a standby current erasion circuit applied in DRAM, which improves prior art word line driving circuit to have the word line voltage outputted in standby mode be equal to the bit line voltage, thereby the short DC standby current between the word line and bit line can be erased.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a circuit for erasing theleakage current of DRAM, more particularly to a circuit for erasing theshort DC standby current between the bit lines and the word lines ofDRAM.

[0003] 2. Background of the Invention

[0004] In the manufacturing process of DRAM, a short circuit between thebit line and the word line sometimes occurs and causes a leakage currentand affect the product yield.

[0005] One of the solutions for the above-mentioned problem is disclosedin U.S. Pat. No. 5,499,211, entitled “BIT-LINE PRE-CHARGE CURRENTLIMITER FOR CMOS DYNAMIC MEMORIES.” As shown in FIG. 1, a conventionalcircuit 10 comprises a word line 12, a pair of complementary bit lines13, a pre-charge equalization circuit 14 and a current-limiting means11. In prior art, in order to prevent an excess leakage current causedby the short circuit between the bit line (BL) and the word line (WL), acurrent-limiting means 11, such as a depletion NMOS, is added between asource of pre-charge voltage (VBLEQ) 15 and the pair of complementarybit lines 13 so as to limit the maximum leakage current when the shortcircuit between the bit line and the word line occurs.

[0006] Generally, the word line voltage (V_(WL)) is 0 volt in thestandby mode, such as the word line driving circuit 20 shown in FIG.2(a). However, the bit line voltage is larger than 0 volt, so a leakagecurrent path will be formed in the standby mode. The leakage currentwill flow from BLEQ, BL, and WL to the ground. FIG. 2(b) shows a timingdiagram of FIG. 1 and FIG. 2(a). In other words, the conventional methodcannot effectively erase the leakage current when the short circuitoccurs between the bit lines and the word lines. For the currentapplication in the product for low power DRAM, the leakage current isstill too large to satisfy the market requirement.

[0007] Regarding the problems in the prior art, the present inventionprovides an innovative standby current erasion circuit for the DRAM toovercome the above-mentioned disadvantages.

SUMMARY OF THE INVENTION

[0008] The object of the present invention is to provide a standbycurrent erasion circuit for DRAM, which is suitable for the applicationrequirement in a low power DRAM.

[0009] To this end, the present invention discloses a standby currenterasion circuit for DRAM, which improves prior art word line drivingcircuit to have the word line voltage output in standby mode be equal tothe bit line voltage, thereby the short DC standby current between theword line and bit line can be erased.

[0010] The standby current erasion circuit for DRAM according to thepresent invention comprises a block detection circuit and a word linedriving circuit. The block detection circuit is used to enable a shortcircuit control signal when a short circuit between the bit lines andword lines of the DRAM is detected. The word line driving circuit isconnected to the block detection circuit, and sets a voltage level ofthe bit line occurring a short circuit as a voltage level of thecorresponding word line occurring a short circuit in a standby mode ifthe short circuit control signal is enabled.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention will be described according to the appendeddrawings in which:

[0012]FIG. 1 shows a prior art standby current erasion circuit for DRAM;

[0013]FIG. 2(a) shows a prior art word line driving circuit;

[0014]FIG. 2(b) shows a timing diagram of FIG. 1 and FIG. 2(a);

[0015]FIG. 3(a) shows an embodiment of the word line driving circuitaccording to the present invention;

[0016]FIG. 3(b) shows a timing diagram of the invention if there is noshort circuit between the word lines and the bit lines;

[0017]FIG. 3(c) shows a timing diagram of the invention if a shortcircuit occurs between the word lines and the bit lines;

[0018]FIG. 4(a) shows an embodiment of the word line driving circuit ofFIG. 3(a) according to the present invention;

[0019]FIG. 4(b) shows a timing diagram of the word line driving circuitof FIG. 4(a);

[0020]FIG. 5(a) shows an embodiment of the inverters of FIG. 4(a);

[0021]FIG. 5(b) shows a timing diagram of the structure in FIG. 5(a);

[0022]FIG. 6(a) shows an embodiment of the first logic circuit of FIG.4(a);

[0023]FIG. 6(b) shows a timing diagram of the structure in FIG. 6(a);and

[0024]FIG. 7 shows an embodiment of the second logic circuit of FIG.4(a).

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

[0025] The standby current erasion circuit for DRAM according to thepresent invention can adopt a structure similar to FIG. 1. The detaileddescription is illustrated as follows.

[0026]FIG. 3(a) shows an embodiment of the word line driving circuitaccording to the present invention. This embodiment inserts a blockdetection circuit 31 in a front stage of prior art word line drivingcircuit (e.g., an inverter), and pulls up the word line driving voltageV_(WL) from 0 V to the bit line voltage V_(BL). FIG. 3(b) shows a timingdiagram of the invention if there is no short circuit between the wordlines and the bit lines, and FIG. 3(c) shows a timing diagram of theinvention if a short circuit occurs between the word lines and the bitlines. When there is no short circuit between the bit lines and wordlines, a selection line S is set to zero; or one, otherwise. The blockdetection circuit 31 functions like a decoder, and when the selectionline S is zero, the output signal A is equal to the input signal IN. Inother words, in this situation, the signal feeds through the blockdetection circuit 31. However, when the selection line S is one, theblock detection circuit 31 inverts the input signal IN to obtain theoutput signal A. In other words, the output signal A functions as ashort circuit control signal. By the circuit of the invention, a shortDC standby current due to manufacturing flaws will be erased, and therequirements of low power DRAM products will be satisfied.

[0027] In addition, since the output voltage of the word line drivingcircuit occurring a short circuit in a standby mode is equal to the wordline voltage, the leakage current due to a short circuit between theword lines and bit lines can be erased. In other words, the presentinvention can omit the current-limiting means 11 used in prior art andget a better performance.

[0028]FIG. 4(a) shows an embodiment of the word line driving circuit ofFIG. 3(a) according to the present invention. By a first logic circuit41, a second logic circuit 42, an inverter 43 and a fuse 44, theselection line S and the input signal IN can generate output signals Aand WL, and the signal EQ serves as a control signal for shiftingvoltage level. FIG. 4(b) shows a timing diagram of the word line drivingcircuit of FIG. 4(a).

[0029]FIG. 5(a) shows an embodiment of the inverters 43 of FIG. 4(a). Bythe fuse 44 and spare circuits on columns and rows of the DRAM, theproblem of short circuits between word lines and bit lines can besolved. FIG. 5(b) shows a timing diagram of the structure in FIG. 5(a).

[0030]FIG. 6(a) shows an embodiment of the first logic circuit 41 ofFIG. 4(a), and FIG. 6(b) shows a timing diagram of the structure in FIG.6(a).

[0031]FIG. 7 shows an embodiment of the second logic circuit 42 of FIG.4(a).

[0032] The above-described embodiments of the present invention areintended to be illustrative only. Numerous alternative embodiments maybe devised by those skilled in the art without departing from the scopeof the following claims.

What is claimed is:
 1. A short DC standby current erasion circuit ofDRAM, comprising: a block detection circuit for enabling a short circuitcontrol signal when a short circuit between bit lines and word lines ofsaid DRAM is detected; and a word line driving circuit connected to saidblock detection circuit, said word line driving circuit setting avoltage level of the bit line occurring a short circuit as a voltagelevel of the corresponding word line occurring a short circuit in astandby mode if said short circuit control signal is enabled.
 2. Theshort DC standby current erasion circuit of claim 1, wherein said blockdetection circuit is a decoding circuit.
 3. The short DC standby currenterasion circuit of claim 2, wherein said block detection circuitcomprises a fuse, a first logic circuit and a second logic circuit. 4.The short DC standby current erasion circuit of claim 1, wherein saidword line driving circuit is an inverter.
 5. The short DC standbycurrent erasion circuit of claim 1, wherein said word line drivingcircuit comprises a plurality of spare inverters.
 6. A short DC standbycurrent erasion circuit of DRAM, comprising a plurality of word lines, aplurality of complementary bit lines, a plurality of pre-chargeequalization circuits and a plurality of word line driving circuits,characterized in that said word line driving circuits can detect if ashort circuit occurs between the plurality of word lines and theplurality of complementary bit lines, and said word line drivingcircuits set a voltage level of the word line occurring a short circuitas a voltage level of the corresponding bit line occurring a shortcircuit in a standby mode for erasing a short DC standby current betweenthe bit lines and the word lines.
 7. The short DC standby currenterasion circuit of claim 6, wherein the plurality of word line drivingcircuits are inverter circuits.
 8. The short DC standby current erasioncircuit of claim 6, wherein each of the plurality of word line drivingcircuits includes a block detection circuit for detecting if a shortcircuit occurs between said bit lines and word lines.